1. Field of the Invention
The invention relates to a semiconductor memory device, and more particularly to a dynamic random access (DRAM) memory device including multiple logical value memory cells.
2. Description of the Related Art
There has been suggested a multiple logical value type DRAM where a memory cell stores 2.sup.N number of charge conditions therein to thereby store N bit data therein, in order to enhance bit integration in DRAM. In such a logical value type DRAM, (2.sup.N -1) number of reference voltages are compared to voltages read out of a memory cell by means of a sense amplifier to thereby read 2.sup.N number of charge conditions as a voltage signal.
For instance, FIG. 1 illustrates a relation between reference voltages and a voltage signal read out of a memory cell when N is equal to two (N=2). In order to make it possible to read four logical values, it is necessary to prepare three reference voltages (2.sup.N -1=2.sup.2 -1=3). For instance, it would be necessary to prepare three reference voltages, Vcc/6, Vcc/2 and 5 Vcc/6, between 0 V and Vcc in order to read four logical values 00, 01, 10 and 11. In FIG. 1, each of the three reference voltages is represented with a broken line.
Japanese Unexamined Patent Publication No. 63-149900 has suggested a reading circuit used in such a semiconductor memory device as mentioned above where N=2. FIG. 2 illustrates a circuit diagram of the suggested reading circuit. As illustrated, in the suggested semiconductor memory, a complementary pair of bit lines BL and BLB are almost equally divided into three pieces to thereby make three complementary pairs of divided bit lines BL1, BL2, BL3 and BL1B, BL2B, BL3B. The divided bit lines BL1 and BL1B constituting a complementary pair are electrically connected through a transfer switch SWT. Similarly, the divided bit lines BL2, BL2B and BL3, BL3B are electrically connected through transfer switches SWT, respectively. Each of the bit lines pairs BLi and BliB (i=1, 2 or 3) is provided with a sense amplifier SAi, a word line WLi, and complementary dummy word lines DWLi and DWLiB for producing reference voltages.
Hereinbelow is explained the operation of the above-mentioned semiconductor memory with reference to FIGS. 1 and 2. In pre-charged condition, the word line WLi and the dummy word lines DWLi and DWLiB are kept at level zero (0), the transfer switches SWT are turned on, and the divided bit line pairs are pre-charged at Vcc/2. Then, a selected word line WLi is turned to level one (1), and data stored in a cell connected to the selected word line is read out. Since all the transfer switches SWT are turned on, read-out signals are transmitted to the entire divided bit line pairs BLi and BLiB (i=1, 2, or 3), even if whichever memory cell is read out.
Then, all the transfer switches SWT are turned off, and one of the dummy word lines DWLi and DWLiB is selected. Then, reference voltages as illustrated in FIG. 1 are applied to the divided bit lines from which read-out signals are not transmitted. For instance, the reference voltages Vcc/6, Vcc/2 and 5 Vcc/6 are applied to the divided bit lines BL1, BL2 and BL3, respectively.
Then, all the sense amplifiers SAi are activated. As a result, the divided bit lines BLi and BLiB would have either 1 level when a voltage thereof is higher than the applied reference voltage, or 0 level when a voltage thereof is lower than the applied reference voltage. The thus obtained logical values, 1 or 0 level, are input to a circuit for encoding the logical values into two bit values in accordance with a logical value table as shown in Table 1.
TABLE 1 ______________________________________ BL1 BL2 BL3 OUT 1 OUT 2 ______________________________________ 0 0 0 0 0 1 0 0 0 1 1 1 0 1 0 1 1 1 1 1 ______________________________________
As mentioned earlier, data is read out by comparing a read out voltage to a reference voltage in a conventional multiple logical value type DRAM. Accordingly, it would be necessary to prepare (2.sup.N -2) number of writing voltages and (2.sup.N -1) number of reference voltages separately from a ground voltage 0 V and a source voltage Vcc in order to cause a memory cell to store N bit data therein. A difference between adjacent reference voltages is equal to Vcc/2(2N-1)!. In the above-mentioned case wherein N=2, a difference between the reference voltages is equal to Vcc/6. Hence, it would be necessary in the above-mentioned conventional DRAM to exactly generate in DRAM chip a plurality of voltages having a small difference between one another.
In addition, as the conventional DRAM has a quite complicated structure, it would be quite difficult or almost impossible to reduce a chip area. For instance, the above-mentioned conventional DRAM carries out a complicated operation as follows. As mentioned earlier, the bit lines are divided for each of the sense amplifiers. After data has been read out of a pair of bit lines, sensing operation is carried out for each of the divided bit lines, and then results of the sense amplifiers associated with the divided bit line pairs are input into an encoder to thereby obtain desired results.
The conventional DRAM has another problem that it would be almost impossible to use the circuit therefor, if the different number of read logical values are desired to obtain. For using the circuit in the conventional DRAM for obtaining the different number of read logical values, all of the number of division in bit lines, number and values of reference voltages, and an encoding circuit for dealing with results from sense amplifiers have to be altered. Accordingly, a reading circuit has to be designed to have a different structure for the different number of logical values to be obtained.
As mentioned earlier, data is read out by comparing a read-out voltage to reference voltages in the above-mentioned semiconductor memory. Hence, differences between writing voltages and between reference voltages are unavoidable to be quite small when multiple logical values are to be obtained, and thus it is absolutely necessary to exactly generate in DRAM chip a plurality of voltages having a quite small difference between one another, which increases difficulty in fabricating DRAM.
In addition, the conventional DRAM has a problem that it is almost impossible to reduce a chip area due to complexity of a circuit structure. The conventional DRAM has another problem that it is quite difficult or almost impossible to use a circuit pattern in DRAM for obtaining the different number of read logical values, because the number of division in a bit line, the number and values of reference voltages, and a circuit for sense amplifiers are all necessary to be altered.